我正在尝试在 Cyclone V FPGA 上实现一个 Time-to-Digital Converter。我正在使用 Quartus Prime 17.1 lite 版本 (No license)。我在操纵放置和路由时遇到麻烦。我想要实现的连接在图像 1 中描绘。这个想法是一个参考信号 (Propogated Signal) 通过使用进位链连接的嵌入式加法器延迟。我想通过捕获下降和上升沿的加法器的输出
image1我用于描述加法器级联的代码是：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity unsigned_adder is
generic
(DATA_WIDTH : natural := 8 );
port
( input_signal : in std_logic;
a : in std_logic_vector ((DATA_WIDTH-1) downto 0);
b : in std_logic_vector ((DATA_WIDTH-1) downto 0);
result : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end entity;
architecture rtl of unsigned_adder is
begin
result <= a + b + input_signal;
end rtl;
为了生成 FFD 集，我尝试了三种不同的方法来描述 FFDS；第一个是使用 Quartus II 手册中推荐的 HDL 编码样式中所示的代码样式，与 Cyclone V 架构中物理上现有的 FFD 相匹配。第二个使用 DFFEAS 原语，第三个是描述 FFD 的一般样式。代码如下所示：
library ieee;
use ieee.std_logic_1164.all;
-- Add the library and use clauses before the design unit declaration
library altera;
use altera.altera_primitives_components.all;
entity FFX is
generic(capture_edge : integer := 1 -- Rising => 1 -- Falling => 0
);
port
(iclk : in std_logic;
irst : in std_logic;
ien : in std_logic;
D_data : in std_logic;
Q_data : out std_logic
);
end entity;
architecture rtl of FFX is
BEGIN
-- --FIRST METHOD -------------------------------------------------------
--Rising_sel : if capture_edge = 1 generate
-- PROCESS (clk, aclr, sload, sdata)
-- BEGIN
-- IF (aclr = '1') THEN
-- q <= '0';
-- ELSE
-- IF (clk = '1' AND clk'event) THEN
-- IF (ena ='1') THEN
-- IF (sclr = '1') THEN
-- q <= '0';
-- ELSIF (sload = '1') THEN
-- q <= sdata;
-- ELSE
-- q <= data;
-- END IF;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--end generate;
--
--Falling_sel : if capture_edge = 0 generate
-- PROCESS (clk, aclr, sload, sdata)
-- BEGIN
-- IF (aclr = '1') THEN
-- q <= '0';
-- ELSE
-- IF (clk = '0' AND clk'event) THEN
-- IF (ena ='1') THEN
-- IF (sclr = '1') THEN
-- q <= '0';
-- ELSIF (sload = '1') THEN
-- q <= sdata;
-- ELSE
-- q <= data;
-- END IF;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--end generate;
-- --SECOND METHOD -------------------------------------------------------
Rising_sel : if capture_edge = 1 generate
SRFFE_R : DFFEAS
port map (
d => D_data,
clk => iclk,
clrn => '1',
prn => '1',
ena => ien,
asdata => '0',
aload => '0',
sclr => irst,
sload => '0',
q => Q_data
);
end generate;
Falling_sel : if capture_edge = 0 generate
SRFFE_F : DFFEAS
port map (
d => D_data,
clk => not iclk,
clrn => '1',
prn => '1',
ena => ien,
asdata => '0',
aload => '0',
sclr => irst,
sload => '0',
q => Q_data
);
end generate;
-- --THIRD METHOD -------------------------------------------------------
-- Rising_sel : if capture_edge = 1 generate
-- process(irst, iclk) begin
-- if irst = '0' then
-- if rising_edge(iclk) then
-- if ien = '1' then
-- Q_data <= D_data;
-- end if;
-- end if;
-- else
-- Q_data <= '0';
-- end if;
-- end process;
-- end generate;
--
-- Falling_sel : if capture_edge = 0 generate
-- process(irst, iclk) begin
-- if irst = '0' then
-- if falling_edge(iclk) then
-- if ien = '1' then
-- Q_data <= D_data;
-- end if;
-- end if;
-- else
-- Q_data <= '0';
-- end if;
-- end process;
-- end generate;
end rtl;
我使用的是一个组件，其中 FFD 触发下降和上升沿被实例化。参数“No_bits”等于加法器的数量：
library ieee;
use ieee.std_logic_1164.all;
entity Capture_Array is
generic(No_bits : integer := 8
);
port
(iclk : in std_logic;
D_data : in std_logic_vector(No_bits-1 downto 0);
Q_dataRising : out std_logic_vector(No_bits-1 downto 0);
Q_dataFalling : out std_logic_vector(No_bits-1 downto 0)
);
end entity;
architecture rtl of Capture_Array is
component FFX is
generic(capture_edge : integer := 1 -- Rising => 1 -- Falling => 0
);
port
(iclk : in std_logic;
irst : in std_logic;
ien : in std_logic;
D_data : in std_logic;
Q_data : out std_logic
);
END component;
signal xDFF_Rising, xQFF_Rising : std_logic_vector(No_bits-1 downto 0);
signal xDFF_Falling, xQFF_Falling : std_logic_vector(No_bits-1 downto 0);
begin
FFR_FFDs : for i in 0 to No_bits-1 generate
FFX_cmp1 : FFX generic map (capture_edge => 1)
port map (iclk => iclk,
irst => '0',
ien => '1',
D_data => xDFF_Rising(i),
Q_data => xQFF_Rising(i)
);
end generate;
FFF_FFDs : for i in 0 to No_bits-1 generate
FFX_cmp0 : FFX generic map (capture_edge => 0)
port map (iclk => iclk,
irst => '0',
ien => '1',
D_data => xDFF_Falling(i),
Q_data => xQFF_Falling(i)
);
end generate;
xDFF_Rising <= D_data;
Q_dataRising <= xQFF_Rising;
xDFF_Falling <= D_data;
Q_dataFalling <= xQFF_Falling;
end rtl;
最后，我将加法器组件与 FFD 组件连接如下：
Delay_cmp : unsigned_adder generic map (DATA_WIDTH => Length_delay
)
port map
(
input_signal => xLaunchedSignal,
a => (others => '0'),
b => (others => '1'),
result => xresult
);
Captures_cmp : for i in 0 to No_captures-1 generate
Capture_Array_cmp : Capture_Array generic map (No_bits => Length_delay
)
port map
(iclk => icaptures(i),
D_data => xresult,
Q_dataRising => oFine_Measurements_R(i),
Q_dataFalling => oFine_Measurements_F(i)
);
end generate;
出于怀疑的目的，可以鄙视“for generate”。现在，我目前在“芯片规划器”工具中使用拖放方法实现的是图像 2 中所示的连接。该工具不允许我像图像 1 中那样连接我的元素；这是由于（我认为）存在“〜 fedder 逻辑”（图像 3），这是我想消除的东西。我不知道如何（为什么）创建这个逻辑。
Image2 Image3此外，我已经尝试在.qsf 文件中放置 TCL 命令，但由于馈线，它会创建异构路由。
set_location_ignment LABCELL_X13_Y6_N0 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|unsigned_adder:Delay_cmp|result[0]"
set_location_ignment FF_X13_Y6_N1 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:0:FFX_cmp0"
set_location_ignment FF_X13_Y6_N4 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:1:FFX_cmp0"
set_location_ignment FF_X13_Y6_N7 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:2:FFX_cmp0"
set_location_ignment FF_X13_Y6_N10 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:3:FFX_cmp0"
set_location_ignment FF_X13_Y6_N13 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:4:FFX_cmp0"
set_location_ignment FF_X13_Y6_N16 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:5:FFX_cmp0"
set_location_ignment FF_X13_Y6_N19 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:6:FFX_cmp0"
set_location_ignment FF_X13_Y6_N22 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:7:FFX_cmp0"
set_location_ignment FF_X13_Y6_N25 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:8:FFX_cmp0"
set_location_ignment FF_X13_Y6_N28 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFF_FFDs:9:FFX_cmp0"
set_location_ignment FF_X14_Y6_N2 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:0:FFX_cmp1"
set_location_ignment FF_X14_Y6_N5 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:1:FFX_cmp1"
set_location_ignment FF_X14_Y6_N8 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:2:FFX_cmp1"
set_location_ignment FF_X14_Y6_N11 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:3:FFX_cmp1"
set_location_ignment FF_X14_Y6_N14 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:4:FFX_cmp1"
set_location_ignment FF_X14_Y6_N17 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:5:FFX_cmp1"
set_location_ignment FF_X14_Y6_N20 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:6:FFX_cmp1"
set_location_ignment FF_X14_Y6_N23 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:7:FFX_cmp1"
set_location_ignment FF_X14_Y6_N26 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:8:FFX_cmp1"
set_location_ignment FF_X14_Y6_N29 -to "ChannelNTDC:\\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\\Captures_cmp:0:Capture_Array_cmp|FFX:\\FFR_FFDs:9:FFX_cmp1"
如果我尝试通过 TCL 命令强制将所有 FFD 放置在同一 ALM 列中，即通过 FF_X13_...更改坐标 FF_X14_...，我收到错误消息：
Error (170208): Cannot place 5 nodes into a single ALM
Info (170017): Cannot place nodes in a single ALM -- the ALM would be illegal because not all of the LUT and FF inputs are routable.
Info (170072): List of 5 nodes in the ALM
Info (170000): Node "ChannelNTDC:\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|unsigned_adder:Delay_cmp|result[0]"
Info (170000): Node "ChannelNTDC:\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\Captures_cmp:0:Capture_Array_cmp|FFX:\FFF_FFDs:0:FFX_cmp0|\Falling_sel:SRFFE_F"
Info (170000): Node "ChannelNTDC:\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\Captures_cmp:0:Capture_Array_cmp|FFX:\FFR_FFDs:0:FFX_cmp1|\Rising_sel:SRFFE_R"
Info (170000): Node "ChannelNTDC:\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\Captures_cmp:0:Capture_Array_cmp|FFX:\FFF_FFDs:1:FFX_cmp0|\Falling_sel:SRFFE_F"
Info (170000): Node "ChannelNTDC:\Channels:0:ChannelNTDC_cmp|Fine_interpolator:Fine_interpolator_cmp|Capture_Array:\Captures_cmp:0:Capture_Array_cmp|FFX:\FFR_FFDs:1:FFX_cmp1|\Rising_sel:SRFFE_R"
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
如何消除“馈线逻辑”?用于手动操作路由的策略 / 工具是什么?
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